It took me 2+ years to get to this point- on and off, and parts of it definitely beyond my control.
But the MachXO2 family of FPGAs now has a full (experimental) FOSS flow from Verilog to bitstream. I'd upload video, but attachment limits. So see here: https://twitter.com/cr1901/status/1356042679608606721?s=19
Sincere thanks to:
* Dave Shah for nextpnr/prjtrellis help- much of it was reusable.
* Joe Fitz and Tim Ansell for support.
* Andres Navarro for REing the compression algorithm required to program the internal flash of MachXO2 parts. I didn't want to do it and he saved me the trouble.
This milestone would NOT have happened without all their help.
If you wish to try this yourself, you need:
* My yosys fork: https://github.com/cr1901/yosys/tree/machxo2
* My prjtrellis fork: https://github.com/cr1901/prjtrellis/tree/facade
* My nextpnr fork: https://github.com/cr1901/nextpnr/tree/machxo2
The yosys one is probably okay for merging back upstream, but holding off for now. Please be aware of breakage, like "as of this writing, the left and right I/O banks aren't added to the routing graph properly :)" and "you can have any voltage standard, as long as its LVCMOS33 :D".
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