The results of this tool will be a Verilog module which Yosys can synthesize, but being higher-level, I'm hoping it'll make me a more efficient coder.
@ekaitz_zarraga @Shamar I'm also hoping that it'll make migrating to a fully pipelined processor architecture (tentatively called KCP53010) simpler as well, since it apparently has built-in pipelining primitives in its library. They're undocumented at the moment, but I hope to learn more about them in the future.
I didn't know that nMigen stuff. I've some tools of Python -> Verilog compilation but I don't know if they were this. They were quite in an alpha stage anyways when I checked...
Keep us informed with your investigations, looks really interesting project and much harder than what I'm capable of doing :D
@ekaitz_zarraga @Shamar In terms of being difficult, I'd say the bulk of the difficulty comes from having to keep a perfect accounting of all the small details of concurrently operations in mind at once. Any *individual* piece on its own is usually pretty simple to write (though not necessarily easy to get in a state which passes formal verification). :)
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