Where can you download, modify and share a silicon IP block just like you do, say, with gcc?

Nowhere.

The licenses of mainstream proprietary silicon CAD tools explicitly forbid publishing anything created with them. This is partially due to keep algorithms, such as place-and-route, more secret.

It is like writing a book with a proprietary word processor and then not having permission to publish it for not revealing how the grammar checker works.

Free silicon requires free CAD tools.

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@fsi could you also provide sources to claims like “The licenses of mainstream proprietary silicon CAD tools explicitly forbid publishing anything created with them.” please?

@kmicu

Not all CAD tool vendors publish part or all of their licenses, hence the list below is not exhaustive:
synopsys.com/verification/prot (section 2.2 comma 3)
s3.mentor.com/company/enduser- (section 4.1)

Those using such tools should refer to the text of their licenses directly.

For context, the Synopsys LA §2.2 and item 3 say:

> [ . . . ] when you are granted a license to any Implementation IP, you will have a nonexclusive right to:

> [ . . . ] distribute the Implementation IP in netlist or GDSII format as part of any of your Integrated Designs to any third party that provides foundry services to you, solely for the purpose of having that foundry make physical implementations of one or more of entire Integrated Designs of yours, as long as the third-party foundry is subject to confidentiality obligations regarding the Implementation IP that are no less restrictive than the confidentiality obligations in this agreement [ . . . ]
It's a similar situation to how gcc compilation produces binaries that contain bits and pieces from libgcc, except that the GCC license terms explicitly do *not* make the resulting binary subject to the GPLv3 (on the condition that you don't mix GCC with proprietary plugins). The proprietary silicon IP vendors are far more jealously guarding their designs.

https://www.gnu.org/licenses/gcc-exception-faq.html

@clacke
The Mentor Graphics EULA section 4.1 says:

> [ . . . ] Log files, data files, rule files and script files generated by or for the Software (collectively “Files”), including without limitation files containing Standard Verification Rule Format (“SVRF”) and Tcl Verification Format (“TVF”) which are Mentor Graphics’ trade secret and proprietary syntaxes for expressing process rules, constitute or include confidential information of Mentor Graphics. Customer may share Files with third parties, excluding Mentor Graphics competitors, provided that the confidentiality of such Files is protected by written agreement at least as well as Customer protects other information of a similar nature or importance, but in any case with at least reasonable care. Customer may use Files containing SVRF or TVF only with Mentor Graphics products. Under no circumstances shall Customer use Products or Files or allow their use for the purpose of developing, enhancing or marketing any product that is in any way competitive with Products, or disclose to any third party the results of, or information pertaining to, any benchmark.
Restrictions on use, restrictions on studying, restrictions on sharing, restrictions on reverse-engineering.

Free CAD tools with their own associated silicon implementations would enable people to publicly share chip designs, while sharing today is impossible without mutual NDAs.
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