RISCV spec: We canonically define the NOP as being 32 bits all zeroes, but this coincidentally happens to be the encoding for "add 0 to register 0".

ME: ** Cheering, just goes fuckin nuts **

Update: It's now been explained to me I misread the meaning of "OP-IMM" in this table, and actually RISC-V intentionally defines 0x0 to be an illegal instruction (for safety—so if you execute uninitialized memory you know immediately) and NOP is actually 0x13. (OP-IMM is 0x10, ORed with 0x3, the code for "standard 32-bit instruction space".)

This makes sense, but part of me is sad NOP is so arbitrary. It would have been so cool if they'd found an excuse to make 0x0 be illegal and 0x1 be NOP.

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I take solace in the fact that at least NOP wound up being an "unlucky 13". An unlucky hex, that is

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