And jemalloc is starting to become friendlier to ASLR. So jemalloc + HardenedBSD = I'm in love!
I would like to see #OpenBSD's malloc imported in HardenedBSD along with Daniel Micay's HardenedMalloc.
@lattera @brnrd @pertho @saper @Gargron @keithzg ASLR is what we call in french « usine à gaz », is an outdated concept, and not even fully protecting against ROP. Like canaries & NX bit in PMMU don’t protect 100% against stack and buffer overflows. I have found a simple 100% operationnal solution stopping these 3 problems just by slitghly modifying any microprocessor architecture. I also consider PMMU a outdated concept.
PaX ASLR and PaX NOEXEC changed forever how exploits are written. Now you must chain multiple vulnerabilities together to gain code execution. They can fully kill certain vulnerabilities and attackers must now pay much closer attention to both control and data flow.
The overarching goal of security is to raise the economic cost of a successful and reliable attack.
PaX ASLR and PaX NOExEC do that and with minuscule overhead on the part of the defender.
So, I wouldn't even come close to saying ASLR is an outdated concept.
Those who claim "ASLR is dead!" either:
1. Don't understand just how much ASLR (and its companion, NOEXEC) have changed exploitation.
2. Have an ulterior motive, a snakeoil sales pitch.
3. Don't actively do exploit dev.
4. Have bought the false narratives of university researchers simply looking for more grant money.
5. Don't fully understand what ASLR is meant to protect against.
I just recognized that I might have sounded a bit harsh. I apologize if I did.
I just get annoyed with the "ASLR is dead" fallacy. It does exactly what it was meant to do. I think the non-exploit dev (just regular tech folks) have put ASLR on a pedestal it doesn't deserve, which has now caused a general "ASLR is dead" line of thinking.
ASLR remains strong for what it was designed and architected to do: protect purely remote attacks.
@lattera @brnrd @pertho @saper @Gargron @keithzg I should have phrased my point differently. As it is a complex matter, and as I want to have an honnest discussion with you, let me prepare a text or an audio file explaining my point. To me these concepts are outdated, we can do better, way much better. Will be back to you this evening at tomorrow at last, to precisely explain my point. The only rule I’m asking you for this discussion
Now I think that the lesson is learned.
By the way, the implementation of my solution for a 68k clone on FPGA (representing about 10000 to 20000 lines of VHDL code) should fit in about 500 lines of additionnal VHDL code, 1000 lines max, according to me. This is what I call a simple and efficient solution. How many lines of C code does all those software equivalent
Server run by the main developers of the project It is not focused on any particular niche interest - everyone is welcome as long as you follow our code of conduct!