@ekaitz_zarraga @Shamar The bulk of the hardware currently exists as plain-vanilla Verilog with some formal verification used to confirm proper operation, thanks to the SymbiYosys project.

For the upcoming redesign of the KCP53000 processor, though, I'm going to rewrite it into a higher-level project, .

The results of this tool will be a Verilog module which Yosys can synthesize, but being higher-level, I'm hoping it'll make me a more efficient coder.

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@ekaitz_zarraga @Shamar I'm also hoping that it'll make migrating to a fully pipelined processor architecture (tentatively called KCP53010) simpler as well, since it apparently has built-in pipelining primitives in its library. They're undocumented at the moment, but I hope to learn more about them in the future.

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