@Shamar @vertigo Are you doing the chip with a FPGA or you are using a SoC or a MicroSomething?

@ekaitz_zarraga @Shamar I'm currently planning on using FPGAs for everything. Everything in the Kestrel project is homebrew, including the processor, all under a libre license.

@ekaitz_zarraga @Shamar Right now, I'm targeting the iCE40HX8K FPGAs, but I'm almost certain Yosys will fully supprt the larger ECP5K family as well.

@vertigo @Shamar That's a good thing. We need some support more for linux tools on FPGAs, iCE40s had to reverse engineer the whole process...

What are you using for them? VHDL/Verilog or something more abstract on top like Chisel or so?

@ekaitz_zarraga @Shamar The bulk of the hardware currently exists as plain-vanilla Verilog with some formal verification used to confirm proper operation, thanks to the SymbiYosys project.

For the upcoming redesign of the KCP53000 processor, though, I'm going to rewrite it into a higher-level project, . github.com/m-labs/nmigen

The results of this tool will be a Verilog module which Yosys can synthesize, but being higher-level, I'm hoping it'll make me a more efficient coder.


@ekaitz_zarraga @Shamar I'm also hoping that it'll make migrating to a fully pipelined processor architecture (tentatively called KCP53010) simpler as well, since it apparently has built-in pipelining primitives in its library. They're undocumented at the moment, but I hope to learn more about them in the future.

@vertigo @Shamar Looking good!

I didn't know that nMigen stuff. I've some tools of Python -> Verilog compilation but I don't know if they were this. They were quite in an alpha stage anyways when I checked...
Keep us informed with your investigations, looks really interesting project and much harder than what I'm capable of doing :D

@ekaitz_zarraga @Shamar nMigen seems mature enough to be used on real-world silicon in large physics laboratories, which is where most of its maintainers work currently. That gives me the confidence to give nMigen (and its predecessor Migen) a whirl.

@ekaitz_zarraga @Shamar In terms of being difficult, I'd say the bulk of the difficulty comes from having to keep a perfect accounting of all the small details of concurrently operations in mind at once. Any *individual* piece on its own is usually pretty simple to write (though not necessarily easy to get in a state which passes formal verification). :)

@vertigo @Shamar I only worked on this kind of things at uni but I'm not a EE (I'm a Telecom Engineer) and never worked on this... soooo... too difficult :)

@ekaitz_zarraga @Shamar I do plan on using the hashtag for this particular computer project. If I ever got to working on a Kestrel-4 at all, I'll probably use at that time. Maybe I should also use as well? I guess it doesn't hurt.

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