@email@example.com @firstname.lastname@example.org @theruran The new classes of exploits depend on the behaviors of micro-architectural features that transcend instruction sets: the fact that cache line refill takes time to complete, or speculation across privilege boundaries, and so on. RISC-V, ARM, x86, etc. doesn't matter. Most are susceptable to most exploits, even if we don't know how just yet.
@email@example.com @firstname.lastname@example.org @theruran (I remember both AMD and ARM boasting about how they're not susceptable to Spectre, rah rah rah!! Until they were, and they shut up *real* quick on the matter.)
@email@example.com @theruran I especially mention this because RISC-V is only an instruction set spec. Individual implementations, such as Rocket, BOOM, or my own KCP53000 will have varying degrees of susceptability to things like Spectre, et. al.
My core is built like a 6502, so it has no cache, pipelines, nor out of order execution to speculate with; it's very resistant to exploits. BOOM has all of these features *and* is superscalar; it'll be exploitable with enough effort.
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