@vertigo hey - I stumbled on your SMG project written in Shen, and I didn't realize you'd written any Shen.

Can you tell me more about how you used it? Or what you learned and applied elsewhere? Thanks!


@theruran I'm not sure I can answer your questions, as that's literally the only Shen I've written. :)

@vertigo ah, well, I realized the questions were vague about 'it'. Can you tell me more about the state machine generator? Have you used it a lot?


@theruran So far, I used it only to help produce the 53000 processor design.

SMG is a tool which is used to build "PLA"-type instruction decoders, such as those found in the 6502. You feed it a set of if-this-then-that style expressions, which are all independent from each other (being implemented as asynchronous logic). That allows more than one decoder output to respond to a common set of input conditions.

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@theruran This differs from traditional state machine decoding in Verilog, which is typically synthesized as priority decoders, so you get one and only one "hot" output.

You can still work with this style of decoder, but it's more verbose and error-prone.

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