Right now, the "official" RISC-V reference implementation, Rocket, is still ASIC-optimized. FPGA-based RISC-V cores tend to be home-grown things these days.
You can still synthesize Rocket on an FPGA, but because it's optimized for ASICs, it needs a rather large FPGA to do so, since it's investing individual LUTs to things that can be only a few transistors in an ASIC.
That said, I do know that:
- Rocket core, KCP53000, and PicoRV32 are *not* susceptible to either Meltdown nor Spectre
- BOOM core, as it currently stands, *IS* susceptible to Spectre, but not to Meltdown.
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