today I've been reading Intel datasheets for recent chipsets and I've learned *so many* interesting things! turns out I can just go and read one for my laptop and then poke it, who'd have thought
TIL Intel didn't actually remove the A20 gate support in Haswell, they just virtualized the physical A20M# *wire*: https://mastodon.social/media/i9uvCNnVkiMA48sXyh8
TIL Intel ME can communicate over Ethernet while the PC is turned off by encapsulating Ethernet packets in SMBus (aka I2C) packets to the PHY, in a really awkward way https://mastodon.social/media/qAZWVwTpIrq1q3N8NSc
... and this leaves to some really awkward things, like a GbE PHY being connected to PCH via a half-rate link that's PCIe electrically but actually transmits raw Ethernet frames https://mastodon.social/media/QJCjbUFC-OYrZqFksq0
TIL the way Intel lets the firmware prevent the OS from modifying certain GPIOs is... well... this is embarrassing really
https://mastodon.social/media/aLNbt-Jvoh8Vmh_3urw
@whitequark modern computers are fuckin' wild.
I mean, old ones are too, but in a completely different way.
TIL pressing the reset button does not actually reset the system immediately https://mastodon.social/media/ZmX9EBuACJBix7PTzQE
TIL not only the CPU will underclock itself under high load, but the PCH will *reduce the number of active data lanes* to the CPU under high load (and also underclock ME because of *course* badly written ME firmware can cause PCH to overheat) https://mastodon.social/media/kDQzXwP8AQVWjLCfifA
@whitequark what are these horrors
what are you reading??
apparently Intel ME debug mode can be enabled by pulling up... the audio codec data line?! Did someone look back at the A20 gate and think "what a brilliant idea"? https://mastodon.social/media/8dtBery6qC-H30NIuu0 https://mastodon.social/media/nN5HWqj15KVeVT3C1go
@whitequark ............oh good grief.
@munin @whitequark Just retootedliterally all of that.
Sorry not sorry. Jesus fuck tho... 🙃
@whitequark come on 16 miliseconds... just to make sure the button is really pressed and it was not your cat.
find that part of spec that says 3 seconds button press is a real power off and not soft ACPI "power off" signal
Which doc are you quoting exactly?
@saper debouncing is not what I'm talking about, waiting for SMBus transactions (and also a 4-second timeout on memory transactions, see the next toot) is. I'm quoting Intel document number 332690-004
@whitequark @scanlime I hate computers
@whitequark WHYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYYY
It's for WOL I'm sure, but good -grief-
TIL recent Intel chipsets heavily multiplex all external I/O; the choice of which channel implementing which protocol is read from the SPI flash (the same where firmware lives) before deasserting CPU reset
https://mastodon.social/media/FUug9Bn429vAJ9pHKCs