I really start to like #uxn and #varvara. It's such a minimalist architecture and it's also open source and open standard.

If I have enough time I'll make a "doom's day" computer in #verilog and I'll probably buy one of those small #FPGAs from #Olimex.

#FPGAs are the #TTL of the 2010s `Send Toot`

Fearlessly generate your own clocks with Lattice ECP5 #FPGAs and Yosys. Includes worked examples for #ULX3S and easy to adapt to any dev board. Happy #FPGAFriday! @yosyshq https://projectf.io/posts/ecp5-fpga-clock/

In 2001 i demonstrated mpeg core synthesis (admittedly targetting asic) in a conference (stupid idea).

in the era of #FPGAs, slightly annoyed that i can't upgrade my dab radio to dab+(mpeg codec change), but yes, i know there are different front-end bandwidths and other things that will constrain this.

and every single part of it is possible in software defined radio.

so now i've maybe gone down the rabbithole of just making a dab+ radio.

Hello everyone. On this account, I want to share my experience with #FPGAs and digital circuit development in general. My colleagues and I have also started a blog https://fpgahero.com where we will occasionally write posts on this topic. Stay tuned. #FPGA #blog #introduction

@jgkoomey @geerlingguy @film_girl
This is a subject super near and dear to me. I now basically work on #asics and to a much lesser degree #fpgas but in the time around when the M1 came out was a string of R&D programs I started on that got cancelled in succession for "limited business viability" reasons.

#FPGAs aren’t scary!

youtu.be/plXJ4s4tk…

We just drop a new TornadoVM version, 1.0.8 with improvements and many fixes. This version expands the profiler of the LevelZero/SPIRV backend with power metrics, new API calls for log and debug execution plans, fixes for running on OSx 14.6 and more!

Check it out!
https://github.com/beehive-lab/TornadoVM/releases/tag/v1.0.8

Anyone here knowledgeable about #FPGAs that I could chat to if i have questions?

The 1942 core is now working on #Xilinx #FPGAs on the #MiSTeX #retrogaming platform.
Thanks to the fantastic work of @somhi (on GitHub),
I could write a shell script which automates most of the gruntwork of the porting process.
This is the first one ported with that script.
I did the script and this port in a couple of hours.

Which #FPGA vendor do you prefer? Feel free to explain why in the comments. Thanks for every boost! #FPGAs #fpgafriday #fpgawars

The new #Quartus Pro 24.1 will be released soon.The new feature will support #FPGAs from #Agilex 5 series by #Altera and will probably not require a paid license. It was mentioned on Reddit: https://www.reddit.com/r/FPGA/comments/1bnvua0/comment/kwmb8r7/?utm_source=share&utm_medium=mweb3x&utm_name=mweb3xcss&utm_term=1&utm_content=share_button

My project spi-fpga is available on Github for many years and is gradually collecting stars. It is just a simple #SPI controller for #FPGAs written in #VHDL, so I didn't expect 156 stars. https://github.com/jakubcabal/spi-fpga

This week's work. Implement dynamic reconfiguration core for #Xilinx #FPGAs. Integrate into #MiSTeX #opensource #retrogames #console. Now changing video modes and #HDMI works with Xilinx FPGAs for the first time. Up to 1366x768@60. FullHD not yet. Hope for the new board revision.
VGA works with 1080p.

RT MicrochipTech: Our FPGAs address the high-reliability requirements of high-availability, safety-critical and mission-critical systems in a variety of applications. Information: https://www.microchip.com/en-us/products/fpgas-and-plds/reliability?utm_campaign=fpga-reliability-requirements&utm_source=twitter.com&utm_medium=Post&utm_content=SharePoint45282.5833. #FPGAs #Reliability #SafetyCritical #Aviation #industrial https://twitter.com/MicrochipTech/status/1738303435785826741photo/1

RT MicrochipTech: New horizons are open for developers, tinkerers and the open source community to explore the vast potential of RISC-V architecture and FPGA technology: https://www.beagleboard.org/blog/2023-11-02-beaglev-fire-announcement. BeagleBoard.org #RISCV #FPGAs #PolarFire #SoC #Opensource #BeagleVFire https://twitter.com/MicrochipTech/status/1737941012889407731photo/1

RT MicrochipTech: Learn about the architectural details of the most recent FPGA families, target applications, available IP blocks, microprocessor cores, development tools and the design ecosystem to implement designs. Register for FREE: https://mu.microchip.com/hello-fpga?utm_campaign=microchip-university-december-courses&utm_source=twitter.com&utm_medium=Post&utm_content=SharePoint45271.5833. #FPGAs #designecosystem https://twitter.com/MicrochipTech/status/1733954747600871917photo/1

RT MicrochipTech: Get to market quickly with a compact and powerful PolarFire® FPGA SoC System on Module (SoM). Details on the blog: https://www.microchip.com/en-us/about/media-center/blog/2023/quick-time-to-market-with-polarfire-soc-fpga-som?utm_campaign=polarfire-fpga-som&utm_source=twitter.com&utm_medium=Post&utm_content=SharePoint45248.3333. Enclustra #RISCV #PolarFire #FPGAs #SystemonModule #SoC https://twitter.com/MicrochipTech/status/1725891690899419272photo/1

It turns out that it is reasonable to build a #uxn cpu on the lattice ICE40 family of #fpgas. They have 64K words of 16 bit memory, but one can access just he first 8 bits of each word.. One could use just half the memory, and access just one byte at each address.

RT from MicrochipTech (@MicrochipTech)

We can support the development of your projects using our RISC-V SoC FPGAs and soft CPUs. Meet us at the RISC-V Summit through Thursday, November 8, 2023 at the Santa Clara Convention Center (booth D2): https://www.microchip.com/en-us/about/events/risc-v-summit. #RISCVSummit #RISCV #MiVEcosystem #PolarFire #FPGAs

Original tweet: https://twitter.com/MicrochipTech/status/1722056383099768911