# first.items[].content
The #riscv CPU loops over the chessboard, generating the instructions to draw each square, then starts the 2D graphics engine. The CPU can prepare drawings then continue with other things while the graphics engine renders. Here running in Verilator/SDL simulation. #FPGA

# first.items[].contentMap.en
The #riscv CPU loops over the chessboard, generating the instructions to draw each square, then starts the 2D graphics engine. The CPU can prepare drawings then continue with other things while the graphics engine renders. Here running in Verilator/SDL simulation. #FPGA

# first.items[].attachment[].name
Chessboard in purple and light blue running in Verilator/SDL simulation.