William D. Jones @cr1901@mastodon.social

https://www.chess.com/article/view/his-pawn-cheated-and-killed-my-pawn

Okay, this is hilarious, and at the same time there should probably be some message indicating to newbie players that en passant is not cheating.

@er1n (Shh... don't tell anyone, but my UART demo using nextpnr doesn't work yet. Post-synth simulation fails, so I haven't bothered programming the bitstream yet. I'm still working on it...)

@er1n Hi Erin, I have some (n)migen news you might be interested in, since you fav'd the core :D.

I'm probably gonna update my UART core to use nmigen (or provide an option between migen and nmigen) soon, and make sure it works w/ modern fusesoc.

Olof expressed interested in fusesoc for the FOSS MachXO2 flow, and I can use this core as a base.

https://github.com/cr1901/migen_uart

https://www.youtube.com/watch?v=zKa92AeSByo Get this f***ing wizard hat off me you damn dirty human!

https://www.youtube.com/watch?v=5dddnZ6BL50 These are some good stretchy paws...

If you wish to try this yourself, you need:
* My yosys fork: https://github.com/cr1901/yosys/tree/machxo2
* My prjtrellis fork: https://github.com/cr1901/prjtrellis/tree/facade
* My nextpnr fork: https://github.com/cr1901/nextpnr/tree/machxo2

The yosys one is probably okay for merging back upstream, but holding off for now. Please be aware of breakage, like "as of this writing, the left and right I/O banks aren't added to the routing graph properly :)" and "you can have any voltage standard, as long as its LVCMOS33 :D".

Sincere thanks to:

* Dave Shah for nextpnr/prjtrellis help- much of it was reusable.
* Joe Fitz and Tim Ansell for support.
* Andres Navarro for REing the compression algorithm required to program the internal flash of MachXO2 parts. I didn't want to do it and he saved me the trouble.

This milestone would NOT have happened without all their help.

It took me 2+ years to get to this point- on and off, and parts of it definitely beyond my control.

But the MachXO2 family of FPGAs now has a full (experimental) FOSS flow from Verilog to bitstream. I'd upload video, but attachment limits. So see here: https://twitter.com/cr1901/status/1356042679608606721?s=19

https://www.youtube.com/watch?v=R57B9mal1S8 Another Side Quest Kitty for @spun_off