Going to stream programming my #tinytapeout submission for a bit over on https://www.twitch.tv/thezoq2.
Let's see if we can make a single NAND gate do something useful
What is it you may ask? It is a time multiplexed NAND-gate and a giant shift register. Schematically, it looks like this.
Every clock cycle, it can read a value from the top of the shift reg to either the left or right operand, and write an input or the current NAND output back into the shift register.
This is able to emulate any circuit with <880 bits of state+wires, but it won't be fun to program, nor fast.
In the video above, it is acting as an 8 bit shift register with feedback, so in theory, we could build another layer now :D
I also did a time multiplexed nand gate on #tinytapeout 4, but then I didn't have the shift registers so I could only fit 128 bits of state compared to the 880 (in 2 tiles) here.
Of course, the tradeoff is time. Me and a friend think we will be able to fit an RV16I on this, but it will run at literal HZ with the ASIC clocked at MHz
As always, tinytapeout is extremely fun, and it is incredible that we can now get custom chips manufactured just to play around with a stupid idea. And not only that, but doing both so and getting the final chip working is extremely easy thanks to a ton of work by @matthewvenn and team
This means we can now run Spade on hardware written in Spade which is immensely satisfying 
Next up, I guess it's time to get SERV up and running 
to take home the slowest SERV award
@thezoq2 Ok, so what would it take to compile SERV to this thing?
@thezoq2 SERV is also neither fast nor easy to program :)
@olofk I mean, at least you can run risc-v instructions :D I have to manually write a sequence of commands that drive the mux and registers at the right time. Just computing `a & b` requires
C::Delay(1), C::ReadRight, C::Delay(879), C::Write, C::Delay(879), C::ReadBoth, C::Delay(879), C::Write, C::Delay(6), C::Delay(864),
@olofk Oh, that should be very doable! @acqrel has a prototype Yosys backend that we're going to try to get working tomorrow.
With some optimizations we should be able to fit a non-bit serial RV32E on here.
Actually, is there a SERV for the E version? Otherwise there won't be enough bits for the register file
@thezoq2 looks interesting, but I still don't understand this schematic. The two registers seem redundant, are they on different clocks? When is the shift register clocked? What controls the mux?
@lambda The whole circuit is synchronous and the shift register is clocked constantly. The two registers are needed so we can hold on to two different values from the reg, and write them back somewhere else. Their enable signals are controlled external.
The MUX is also controlled externally, in my demos here with an FPGA that feeds control signals to it. This is the big lie about the circuit, it needs a giant memory for its instructions to do anything :D
@thezoq2 ahhhh I see, I was missing the external mux select and enables, now it makes sense :D a very pure representation of computation, basically a serial variant of a Moore/Mealey machine, right?
@lambda Yeah, there is something "pure" here. The whole idea came from my advisor ranting about hardware design and "general purpose designs" and saying things like "if we wanted maximum generality and 100% utilization, we'd just build a time multiplexed nand gate"
Though this shift register version kind of moves away from that idea since the utilization is about 880 times less than 100% in the worst case :D
@thezoq2 there's always a slower serv